This work is focused on characterizing the impact of material based disorder on the properties of graphene based vertical tunneling heterostructures. The motivation and challenges for replacing silicon for low power digital electronics has been presented. The status of the research on graphene based digital electronics is critically reviewed. Scalable methods for synthesizing large area two dimensional materials including graphene, molybdenum disulfide, and hexagonal boron nitride are integrated into a complex CMOS fabrication process to investigate the impact of disorder on the properties of vertical graphene based heterostructures for low power digital electronics. The CMOS fabrication process was found to introduce contaminants in the form of polymeric residues that reduced the lateral conduction of the graphene. Thermal decomposition of the residues resulted in the introduction of defects in the graphene. A chemical etching method utilizing a sacrificial titanium layer removed via HF etching effectively removed the contaminants without damaging the graphene. Dielectric tunneling barriers were deposited by atomic layer deposition (ALD). The composition of the tunneling barrier was experimentally shown to alter the electrical performance of the graphene heterostructure and allows barrier engineering for tailoring the electrical properties of the device. The thickness of the tunneling barrier was shown to control the dominant tunneling mechanism with barriers less than ~3 nm required for direct tunneling. The impact of the graphene on the electrical performance of the device was investigated by using graphene of various domain sizes. No dependence was found on the graphene domain size suggesting the tunneling barrier dielectric or device substrate is limiting the device performance. Following recent reports utilizing exfoliated materials, two dimensional materials (molybdenum disulfide and hexagonal boron nitride) complimentary to graphene were utilized as tunneling dielectrics to further improve the device performance over conventional dielectric materials. The direct synthesis of complimentary two dimensional materials on graphene was shown to introduce defects into the graphene structure and to suppress the electrical properties of the device. Trapping of electrons in the MoS2 defect states was shown to drastically suppress the tunneling current compared to less defective exfoliated materials. Decreasing the synthesis temperature of the MoS2 was shown as a potential pathway for reducing the induced defects in the graphene. A large area synthesized hexagonal boron nitride buffer layer was shown to improve the lateral conduction of the graphene. Contrary to reports of exfoliated materials, the introduction of a hexagonal boron nitride tunneling barrier was shown to reduce the mobility of the graphene due to increased scattering as a result of defects in the hexagonal boron nitride as well as contamination introduced during the transfer process. The lateral conductance of the graphene was shown to be improved in the graphene vertical heterostructure with a hexagonal boron nitride buffer layer, but was insufficient to improve the overall device performance. Improved synthesis methods to reduce the intrinsic defects in the as synthesized hexagonal boron nitride is necessary to further improve the graphene heterostructure performance.
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MATIN Development Team